1. Field of Invention
This invention relates generally to computer data processors and more specifically to clock or timing circuitry of such processors.
2. Discussion of Related Art
Computer data processors are widely used in modern electronic systems. For example, most desktop computers are built around a microprocessor chip. The microprocessor chip is a computer data processor that can be programmed to perform many data processing functions. Microprocessors perform arithmetic operations or logical operations which can be combined into many types of programs, such as those used to do accounting or word processing.
Other computer data processors are designed for specialized functions. One example is a digital signal processor (DSP). A digital signal processor is conceptually similar to a general purpose microprocessor. However, a digital signal processor is configured to quickly perform complex mathematical operations used in processing of digital signals.
One important use of computer data processors is implementing the signal processing and control functions of cellular telephones and other portable electronic devices. Fast computation is important in these applications. Moreover, because these data processors are used in devices that derive power from a battery, it is desirable for the data processors to use as little power as possible.
FIG. 1 shows a high level a block diagram of a computer data processor chip 100. FIG. 1 could represent a general purpose computer data processor or it could represent a special purpose data processor, such as a digital signal processor. Within processor chip 100 is a microprocessor core 110. In operation, microprocessor core 110 reads instructions from memory 112 and then performs functions dictated by the instruction. In many cases, these instructions operate on data that is also stored. When an operation performed by microprocessor core 110 manipulates data, the data is read from memory (e.g., memories 116 and 150) and new data is generally stored in memory after the instruction is executed.
FIG. 1 shows that processor chip 100 includes an on-chip instruction memory unit 112 and an on-chip data memory unit 116. Both the instruction memory unit 112 and data memory unit 116 are controlled by a memory management unit (MMU) 114. Instruction memory unit 112 and data memory unit 116 each contain memory that stores information accessed by microprocessor core 110 as instructions or data, respectively.
However, it is generally impossible to build a processor chip with enough on-chip memory to store all the instructions or all the data needed to run a complex program because of lack of sufficient area. Therefore, integrated circuit 100 includes a memory interface 122 that can read or write instructions or data in off-chip memory 150.
Memory 150 could, for example, be DRAM semiconductor memory located on a printed circuit board on which processor chip 100 also is located. However, memory 150 need not be semiconductor memory. Off-chip memory 150 could be an optical or magnetic disk drive or even a magnetic tape, or some combination of storage elements. Regardless of the specific types of memory used to implement off-chip memory 150, it is likely that access time for the off-chip memory and other peripherals is longer than the access time for on-chip memory.
Processor chip 100 also contains interface circuitry that can interface to other off-chip devices. For example, serial interface 134 is shown. Serial interface 134 communicates with microprocessor core 110 via internal bus interface circuitry 130 and internal bus 138. In many cases, the off-chip devices operate at a lower frequency than microprocessor core 110 and other circuitry on processor chip 100.
It is traditional for a processor chip to contain a clock generator 160 that generates at least two clocks, which we call a CCLK and an SCLK. The CCLK signal is at a higher frequency than the SCLK signal. The CCLK signal provides timing to circuitry in the microprocessor core and related circuitry on the integrated circuit 100 that runs at the same clock rate as the core. In contrast, the SCLK signal is used to clock circuitry that interfaces to external memory and other circuitry that runs at a slower rate.
Traditionally, the CCLK and SCLK signals are synchronized so that circuitry clocked by the CCLK signal can communicate with circuitry clocked by the SCLK signal. Synchronization is achieved by having the SCLK signal derived from the CCLK signal. For example, a clock divider has been used to generate the SCLK from the CCLK signals.
We have recognized that prior art clock generation circuitry could be improved by providing greater flexibility in setting the frequencies of the SCLK and CCLK signals. We have recognized it would also be desirable to have a timing system in which the frequency of either clock might be changed on the fly with no jitter or spurious pulses.